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STLD CSE Internal

Added on , Posted by inventionsbyhamid

STLD - Switching Theory and Logic Design.
Date 7-11-2016
Our internal was taken by Vadthya Sir. Internal was scheduled few days before and took place on the same date as decided by Sir. We made many attempts to postpone the internal giving reasons such as parents are forcing to stay in home due to smog, Chath Pooja etc. but in vain.

Sir asked us to bring class notes copy, observation copy and practical file with us. Marks were divided as follows:

  1. Practical File - 15 marks
  2. Observation Copy & Classnotes - 10 marks
  3. Viva - 15 marks

Students were called in groups of 4 and it took around 15 minutes for each group to finish viva. Questions of different difficulties were asked. Following are some of the questions asked:
Q1. Explain the working of BCD adder.
Q2. What is a register? Difference between Flip Flop and Register?
Q3. Explain Series in Series out register.
Q4. What are minterms and maxterms?
Q5. Explain how SR/JK flip flop works.
Q6. What is race around condition?
Q7. Explain how a multiplexer works.
Q8. Conversion from binary to gray code and vice versa.
Q9. Difference between asynchronous and synchronous circuits. Answer
Note: It is adviced even if you have not made classnotes and observation copy entire semester, make sure you make them one day before and copy around 20-30 pages of class notes and 2-3 experiments observations in observation copy. This will fetch you some marks. Also if you want to cover topics in depth and understand make sure you watch the Neso Academy Lectures.

Suitable for Students in year(s): 2

Suitable for branch(es): CSE, ECE, MECH, EEE, IT, CIVIL, and MAE

College: Govind Ballabh Pant Engineering College(GBPEC)

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